The present invention relates to a method for fabricating nitride semiconductor light-emitting devices which emit light in blue-to-ultraviolet regions.
Currently, light-emitting diodes each using a group III nitride have been widely commercialized for various types of displays, large-scale displays, signal lights, or the like. In addition, white LEDs each composed of a combination of a GaN LED and a fluorescent material have also been commercialized and expected to replace lighting devices used at present provided that the light emission efficiencies thereof will be improved in future.
In general, a group III nitride semiconductor (hereinafter simply referred to as a nitride semiconductor) composed of GaN or the like has been formed on a sapphire substrate as mainstream practice. However, since the sapphire substrate has no conductivity, it is necessary to form a p-type electrode and an n-type electrode on the same plane in a GaN growth layer. This causes the problem of increased series resistance due to an elongated current path and the problem of increased device size.
To solve the foregoing problems, a laser lift-off (hereinafter referred to as LLO) technology has been developed.
The LLO technology is a method which grows a GaN layer on a sapphire substrate and irradiates the side of the GaN layer formed with the sapphire substrate with a laser to thermally decompose the portion of the GaN layer located in proximity to the interface between the GaN layer and the sapphire substrate and thereby separate the sapphire substrate from the GaN layer.
A description will be given herein below to a method for fabricating semiconductor devices according to a first conventional embodiment using the LLO technology with reference to FIGS. 7A to 7F (see Japanese Laid-Open Patent Publication No. 2001-274507).
First, as shown in FIG. 7A, a GaN layer 102 is deposited on a sapphire substrate 101.
Next, as shown in FIG. 7B, an electrode layer 103 is formed on the GaN layer 102 and then insulating films 104 are formed on specified regions of the electrode layer 103.
Next, as shown in FIG. 7C, a Cu plate 105 with a thickness of about 50 μm is formed on the electrode layer 103. In this case, Cu is not plated on the insulating films 104, while the Cu plate 105 having a configuration as shown in FIG. 7C is formed on the electrode layer 103.
Next, as shown in FIG. 7D, a holding metal 106 is formed over the Cu plate 105.
Next, as shown in FIG. 7E, the sapphire substrate 101 is separated from the GaN layer 102 by using the LLO technology. Then, electrode layers 107 are formed on specified regions of the GaN layer 102. Subsequently, the holding metal 106 is separated from the Cu plate 105. In FIG. 7E and also in FIG. 7F, which will be described later, the orientation of the drawing has been vertically inverted from that of the drawing in each of FIGS. 7A to 7D.
Next, as shown in FIG. 7F, the GaN layer 102 is scribed to be cleaved such that individual chips are separated from each other. In this case, since the bonded portion 105a (see FIG. 7F) of the Cu plate 105 is relatively low in bonding strength, the Cu plate 105 is also easily separated by cleaving the GaN layer 102.
A description will be given to a method for fabricating semiconductor devices according to a second conventional embodiment using the LLO technology with reference to FIGS. 8A to 8F (see Japanese Patent Application No. 2002-183919).
First, as shown in FIG. 8A, a GaN layer 202 is deposited on a sapphire substrate 201.
Next, as shown in FIG. 8B, an electrode layer 203 is formed on the GaN layer 202 and then an Au plate 204 with a thickness of 10 μm or more is formed thereon.
Next, as shown in FIG. 8C, the sapphire substrate 201 is separated from the GaN layer 202 by using the LLO technology.
Next, as shown in FIG. 8D, electrode layers 205 are formed on the exposed surface of the GaN layer from which the sapphire substrate 201 has been removed.
Next, as shown in FIG. 8E, a resist pattern 206 is formed on the Au plate 204 and then the Au plate 204 is patterned such that the portion of the Au plate 204 serving as a chip isolation region is removed. In this case, the portion of the Au plate 204 is removed by performing wet etching with respect to the surface of the Au plate 204 opposite to the surface thereof formed with the GaN layer 202.
Next, a shown in FIG. 8F, the resist pattern 206 is removed by organic cleaning. Then, the GaN layer 202 is cleaved or cut by using a dicing blade such that the individual chips are separated from each other.
Thus, the nitride semiconductor devices have been fabricated by using the LLO technology as shown in the foregoing first and second conventional embodiments.
However, the methods for fabricating semiconductor devices according to the first and second conventional embodiments encounter the following problems.
First, in the method for fabricating semiconductor devices according to the first conventional embodiment, the function of the thin-film GaN layer 102 as a holding member is degraded if the bonding strength of the Cu plate 105 is extremely low. Consequently, there are cases where the GaN layer 102 is naturally split in the step of performing cleavage. Since such naturally split chips mostly have rough and uneven surfaces, they cannot be used as devices, which causes a reduction in yield. Conversely, if the bonding strength of the Cu plate 105 is high, there are cases where the Cu plate 105 is not separated even when the thin-film GaN layer 102 is separated by cleavage, which also causes a reduction in yield. Thus, the method for fabricating semiconductor devices according to the first conventional embodiment requires strict control of the bonding strength of the Cu plate.
In the method for fabricating semiconductor devices according to the second conventional embodiment, the resist pattern is formed on the thick-film Au plate 204, as described above with reference to FIG. 8E. If the film thickness of the Au plate 204 is large, however, it is difficult during patterning to recognize a layer serving as an underlie for the Au plate 204 so that mask alignment becomes difficult, which causes a reduction in yield. There are also cases where the thin-film GaN layer 202 is naturally separated at the stage at which the portion of the Au plate 204 serving as the chip isolation region has been removed, which also causes a reduction in yield in the same manner as in the first conventional embodiment. Thus, it is also difficult to achieve a high yield even in accordance with the method for fabricating semiconductor devices according to the second embodiment.